1. Field of the Invention
This invention relates to a semiconductor integrated circuit device and more particularly to a erasable programmable nonvolatile semiconductor memory device.
2. Description of the Related Art
In recent years, a erasable programmable nonvolatile semiconductor memory device is rapidly popularized as a recording medium of a portable electronic device.
In such a nonvolatile semiconductor memory device, a high speed programming operation is strongly required in the digital still camera market, for example. This is because the capacity of the recording medium for storing photographs or the like is rapidly increasing.
In order to meet the above requirement, in the nonvolatile semiconductor memory device, the programming page length is made large and the number of memory cells simultaneously subjected to the programming process is increased, to enhance the programming speed. For example, the page length of a NAND nonvolatile semiconductor memory device is normally set to 512 bytes. For example, the page length is increased to 2 Kbytes, that is, increased by four times. Thus, the programming speed can be enhanced by approximately four times in comparison with a device having the page length of 512 bytes.
A typical example of this type of NAND nonvolatile semiconductor memory device is shown in FIG. 1.
As shown in FIG. 1, a memory cell array and a data latch circuit of 512 bytes are provided as one block and four blocks are arranged in one chip. If the memory capacity is kept unchanged, the number of memory cells contained in one memory cell array can be reduced to ¼ the original value. However, the rate of an area of the data latch circuit of 512 bytes (=4 Kbits) which occupies the whole chip area is high. If the four data latch circuits (2 Kbytes (=16 Kbits)) are arranged or eight data latch circuits (4 Kbytes (=32 Kbits)) are arranged to further enhance the programming speed, the chip area is increased.
Document 1 is provided in which a programming method for enhancing the programming speed, while suppressing an increase in the number of data latch circuits, is described.
In a typical NAND nonvolatile semiconductor memory device, approximately 1000 NAND strings are connected to each bit line. In a programming period, one of the approximately 1000 NAND strings which contains a cell transistor to be programmed is selected. For this, 0V is continuously supplied to the channel of the cell transistor from the data latch circuit so as to supply a sufficient amount of charge (for example, electrons) to the floating gate of the cell transistor, for example. However, the amount of charge injected into the floating gate becomes smaller as the cell transistor is more miniaturized. Therefore, as described in the document 1, a NAND nonvolatile semiconductor memory device in which charges stored in the bit line are injected into the floating gate of the cell transistor is proposed.
As described in document 1, the data latch circuit (page buffer) is arranged at the center of the chip and memory cell arrays are arranged on the upper and lower sides of the data latch circuit. The data programming operation is performed for the upper bank memory cell array and lower bank memory cell array at the same time by using charges stored in bit lines of the upper bank memory cell array and bit lines of the lower bank memory cell array. As a result, the programming operation speed can be enhanced while an increase in the data latch circuit is suppressed.
Document 1: Ken. Takeuchi et al. “A Dual Page Programming Scheme for High-Speed Multi-Gb-Scale NAND Flash Memories” 2000 Symposium on VLSI Circuits Digest of Technical Papers pp. 156–157.